Examples

    See exactly how it works

    Scroll through three live demonstrations: raw performance against GPUs, the compiler transforming operators into hardware, and the full pipeline from PyTorch to VHDL.

    Scroll to explore — the story advances as you scroll

    01 — Performance

    One inference. Two very different waits.

    Menex NPU...
    GPU baseline0.0ms

    Same model, same batch. 10x faster inference, deterministic latency.

    Power draw100%

    50% less power at sustained load.

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    02 — Inside Natural

    Watch the compiler think

    The lowering pass

    One function per operator turns math into hardware. lower_conv2d reads the node — kernel size, parallelism budget — and constructs RTLIR as data: modules, signals, clocked logic. A 1×1 kernel gets a pointwise MAC array; a 5×5 gets a line buffer and sliding window.

    NIR node → RTLIR dataclasses
    Conv2Dk=5×5 par=4lower_conv2d()if k==1×1: pointwiseelse: windowed ◄line_buffer · BRAMsliding_window 5×5MACMACMACMACquantise · saturate · stream

    Skip connections, synchronised

    Residual streams rarely arrive together. Natural inserts skid buffers that hold the early stream until its partner arrives, then adds with saturation and full AXI-Stream backpressure — bit-exact. This is the operator that breaks other FPGA toolchains.

    skid-buffered residual Add
    skid buffer+stream A · arrives earlystream B · through conv branchbit-exact

    Hardware you can steer

    Edit parallelism_factor on any node in the graph editor and the compiler re-plans the hardware: more DSP multipliers, wider datapaths, re-inferred signal widths. Co-design annotations live on the IR — you never touch the HDL by hand.

    parallelism 1 → 4 = 4× DSP
    OnnxGraph — conv1opConv2Dparallelism_factor14dsp_budgetauto▸ re-lowering conv1…hardware planDSP 0DSP 1DSP 2DSP 3bus: 8-bit · 1 lanebus: 8→32-bit · 4 lanesannotations on the IR steer the lowering pass — no HDL edited by hand
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    03 — The compiler

    Follow your model down to silicon

    PyTorchONNXNIRLoweringRTLIRVHDL
    # model.py — unmodified
    class LeNet5(nn.Module):
    self.conv1 = nn.Conv2d(1, 6, 5)
    self.pool  = nn.MaxPool2d(2)
    self.fc2   = nn.Linear(84, 10)

    Your unmodified model.py.

    exported.onnxopset 17
    ConvReluMaxPoolConvReluGemmAdd
    torch.onnx.export() — the only step you run

    One export. The boundary contract.

    conv1reluconv2addargmaxskip connectionhw: par=4 · dsp=auto

    Neural graph + hardware annotations.

    lower_conv2d()
    line_buffer (BRAM)sliding_windowmac_array ×4quantise + saturate

    The proprietary core: operators become hardware.

    Module conv1Module fifoModule topSync @clkAssignRTL as data — width inference · const fold · dead-signal

    RTL as data — optimisation passes rewrite it.

    -- output/conv1.vhd
    entity conv1 is
    port(clk : in std_logic;
    data_in : in signed(7 downto 0);
    process(clk) begin
    if rising_edge(clk) then ...
    ✓ GHDL sim · ✓ bit-exact vs PyTorch

    Human-readable, proven bit-exact before the board.

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